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CY29352
2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * * Output frequency range: 16.67 MHz to 200 MHz Input frequency range: 16.67 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 2% max Output duty cycle variation 11 Clock outputs: Drive up to 22 clock lines LVCMOS reference clock input 125-ps max output-output skew PLL bypass mode Spread Aware Output enable/disable Pin compatible with MPC9352 and MPC952 Industrial temperature range: -40C to +85C 32-Pin 1.0mm TQFP package
Description
The CY29352 is a low voltage high performance 200-MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Function Table. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:22. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 16.67 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Block Diagram
PLL_EN# REFCLK FB_IN
LPF /4 / /6
Pin Configuration
Phase Detector
VCO 200-500MHz
/2
QA0 QA1 QA2 QA3 QA4
VCO_SEL SELC SELB SELA MR/OE# REFCLK AVSS FB_IN 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
VDDQC QC1 QC0 VSS VSS QB3 QB2 VDDQB
VCO_SEL SELA
/4 / /2
CY29352
QB0 QB1
VSS QB1 QB0 VDDQB VDDQA QA4 QA3 VSS
QB2 QB3
/2 / /4
QC0 QC1
SELC MR/OE#
Cypress Semiconductor Corporation Document #: 38-07476 Rev. **
*
3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised March 19, 2003
PLL_EN# AVDD VDD QA0 VSS QA1 QA2 VDDQA
9 10 11 12 13 14 15 16
SELB
CY29352
Pin Description[1]
Pin 6 12, 14, 15, 18, 19 30, 31 8 Name REFCLK QA(0:4) O O O I, PD I/O I, PD Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Reference clock input. Clock output bank A. Clock output bank B. Clock output bank C. Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. VCO divider select input. See Table 2. Master reset/output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Frequency select input, Bank (A:C). See Table 2. 2.5V or 3.3V power supply for bank A output clocks.[2,3] 2.5V or 3.3V power supply for bank B output clocks.[2,3] 2.5V or 3.3V power supply for bank C output clocks.[2,3] 2.5V or 3.3V power supply for PLL.[2,3] 2.5V or 3.3V power supply for core and inputs.[2,3] Analog ground. Common ground. Description
22, 23, 26, 27 QB(0:3) QC(0,1) FB_IN
1 5 9 2, 3, 4 16, 20 21, 25 32 10 11 7 13, 17, 24, 28, 29
VCO_SEL MR/OE# PLL_EN# SEL(A:C) VDDQA VDDQB VDDQC AVDD VDD AVSS VSS
I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply
LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground
Table 1. Frequency Table VCO_SEL 0 0 0 1 1 1 Table 2. Function Table Control VCO_SEL PLL_EN# MR/OE# SELA SELB SELC Default 0 0 0 0 0 0 VCO 0 VCO / 2 1 Feedback Output Divider /2 /4 /6 /2 /4 /6 VCO Input Clock * 2 Input Clock * 4 Input Clock * 6 Input Clock * 4 Input Clock * 8 Input Clock * 12 Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz 33.33 MHz to 83.33 MHz 50 MHz to 125 MHz 25 MHz to 62.5 MHz 16.67 MHz to 41.67 MHz Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz 33.33 MHz to 66.67 MHz 50 MHz to 100 MHz 25 MHz to 50 MHz 16.67 MHz to 33.33 MHz
PLL enabled. The VCO output connects Bypass mode, PLL disabled. The input clock to the output dividers connects to the output dividers Outputs enabled QA = VCO / 4 QB = VCO / 4 QC = VCO / 2 Outputs disabled (three-state), VCO running at its minimum frequency QA = VCO / 6 QB = VCO / 2 QC = VCO / 4
Notes: 1. PD = Internal pull-down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
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CY29352
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non Functional Functional Functional Functional Functional 2000 10 -65 -40 200 150 +150 +85 155 42 105 Functional Relative to VSS Relative to VSS Condition Min. -0.3 2.375 -0.3 -0.3 Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 Unit V V V V V mA mVp-p C C C C/W C/W Volts ppm
DC Parameters (VDD= 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] Output Voltage, High[4] Input Current, Low Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS IOL = 15 mA IOH = -15 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD 5 3 170 4 17 - 20 1.8 -10 100 10 5 1.7 Min. Typ. Max. 0.7 VDD + 0.3 0.6 Unit V V V V A A mA mA mA pF
DC Parameters (VDD= 3.3V 5%, TA = -40C to +85C)
Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] Output Voltage, High[4] Input Current, Low Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA IOH = -24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD 5 3 240 4 2.4 -10 100 10 5 2.0 Condition Min. Typ. Max. 0.8 VDD + 0.3 0.55 0.30 V A A mA mA mA pF Unit V V V
Output Impedance 14 - 17 ZOUT Notes: 4. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 5. Inputs have pull-down resistors that affect the input current. Document #: 38-07476 Rev. ** Page 3 of 8
CY29352
AC Parameters[6] (VDD= 2.5V 5%, TA = -40C to +85C)
Parameter fVCO fin Description VCO Frequency Input Frequency /2 Feedback /4 Feedback /6 Feedback /8 Feedback /12 Feedback Bypass mode (PLL_EN# = 1) frefDC tr , tf fMAX Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.7V to 1.7V /2 Output /4 Output /6 Output /8 Output /12 Output DC tr , tf t() tsk(O) tsk(B) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN, same VDD, does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency tPLZ, HZ tPZL, ZH BW Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) /2 Feedback /4 Feedback /6 Feedback /8 Feedback /12 Feedback tJIT(CC) tJIT(PER) tJIT() tLOCK Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz 150 100 1 ms 2 1 - 1.5 0.6 0.75 0.5 100 300 100 150 ps ps ps 100 50 33.33 25 16.67 47 44 0.1 -100 Condition Min. 200 100 50 33.33 25 16.67 0 25 Typ. Max. 400 200 100 66.67 50 33.33 200 75 1.0 200 100 66.67 50 33.33 53 56 1.0 100 125 175 225 8 10 ns ns MHz ns ps ps ps % % ns MHz Unit MHz MHz
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CY29352
AC Parameters[6] (VDD = 3.3V 5%, TA = -40C to +85C)
Parameter fVCO fin Description VCO Frequency Input Frequency /2 Feedback /4 Feedback /6 Feedback /8 Feedback /12 Feedback Bypass mode (PLL_EN# = 1) frefDC tr , tf fMAX Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.8V to 2.0V /2 Output /4 Output /6 Output /8 Output /12 Output DC tr , tf t() tsk(O) tsk(B) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew fMAX < 100 MHz fMAX > 100 MHz 0.55V to 2.4V TCLK to FB_IN, same VDD, does not include jitter Skew within each Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage tPLZ, HZ tPZL, ZH BW Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) /2 Feedback /4 Feedback /6 Feedback /8 Feedback /12 Feedback tJIT(CC) tJIT(PER) tJIT() Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz 150 100 2 1 - 1.5 0.6 0.75 0.5 100 275 100 150 ps ps ps 100 50 33.33 25 16.67 48 44 0.1 -100 Condition Min. 200 100 50 33.33 25 16.67 0 25 Typ. Max. 500 200 125 83.33 62.5 41.67 200 75 1.0 200 125 83.33 62.5 41.67 52 56 1.0 200 125 175 235 425 8 10 ns ns MHz ns ps ps ps % % ns MHz Unit MHz MHz
Maximum PLL Lock Time 1 ms tLOCK Note: 6. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested.
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CY29352
Pulse Generator Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
LVCMOS_CLK
VDD V DD /2 GND
FB_IN
V DD V DD /2
t()
GND
Figure 2. Propagation Delay t(), static phase offset
V DD
tP
T0
V DD/2 GND
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VD D VDD/2 GND VD D VDD/2
tSK(O)
Figure 4. Output-to-Output Skew, tsk(O)
GND
Ordering Information
Part Number CY29352AI CY29352AIT 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40C to +85C Industrial, -40C to 85C
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CY29352
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-07476 Rev. **
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29352
Document History Page
Document Title:CY29352 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer Document Number: 38-07476 REV. ** ECN No. 124654 Issue Date 03/21/03 Orig. of Change RGL New Data Sheet Description of Change
Document #: 38-07476 Rev. **
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